
I²C-bus repeater with 2-channel buffer, 2.3-3.6V, TSSOP-8 package, supports clock stretching.
The NXP PCA9515ADP is a CMOS I²C-Bus Repeater designed for use in I²C-bus and SMBus systems. It preserves all operating modes and features of the I²C-bus while allowing extension of the bus by buffering both the data (SDA) and clock (SCL) lines, enabling two buses of 400pF capacitance. This overcomes the standard 400pF capacitance limit that restricts device count and bus length, allowing system designers to isolate two halves of a bus, accommodating more devices or longer connections.
The repeater features a 2-channel, bidirectional buffer with an active high repeater enable input, open-drain input/outputs, and lock-up free operation. It supports arbitration and clock stretching across the repeater, and includes powered-off high-impedance I²C pins for safe isolation. Latch-up testing exceeds 100mA, conforming to JEDEC standard JESD78. The output pull-down is set to approximately 0.5V, with input thresholds about 0.07V lower, preventing lock-up conditions.
Specifications
Suitable for communications and networking equipment, this repeater enhances system reliability and flexibility in I²C-bus and SMBus applications.
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