NXP PCA9517ADP Level Translating I2C Bus Repeater, TSSOP-8

The NXP PCA9517ADP is a CMOS integrated circuit designed for level translation between low-voltage (down to 0.9 V) and higher-voltage (2.7 V to 5.5 V) I²C-bus or SMBus applications. It retains all standard I²C operating modes while extending the bus through bidirectional buffering for the data (SDA) and clock (SCL) lines. This enables robust communication across two bus segments, each supporting up to 400 pF of capacitance.

A key feature is its ability to isolate two halves of a bus for both voltage level and capacitive load, offering significant design flexibility. The SDA and SCL pins are overvoltage tolerant and remain high-impedance when the device is unpowered. The port A drivers, which interface with the adjustable lower voltage bus, deliver more current and eliminate static offset voltage. This translates a low signal on the higher-voltage port B into a near 0 V low on port A, perfectly accommodating the smaller voltage swings of lower-voltage logic.

Key Features and Specifications

• Bidirectional Buffering: Two-channel buffer isolates capacitance, permitting 400 pF on either side of the device.
• Compatibility: Fully compatible with I²C-bus and SMBus standards.
• Control: Features an active-high repeater enable input for easy master control.
• Interface: Utilises open-drain input/outputs.
• Reliable Operation: Designed for lock-up free operation, supporting arbitration and clock stretching across the repeater.
• Wide Device Support: Accommodates Standard-mode and Fast-mode I²C-bus devices and supports systems with multiple masters.
• Robust Pins: I²C-bus and enable pins are 5 V tolerant; I²C-bus pins are high-impedance when powered off.
• Quality Assurance: Latch-up testing is performed to JEDEC Standard JESD78, exceeding 100 mA.

This integrated circuit is an essential solution for designers needing to bridge mixed-voltage I²